Many computer systems include volatile and non-volatile memory devices. Volatile memory is generally used to store data that a system may need to exchange quickly, such as data used by a computer program. Volatile memory loses its data when power is removed. Examples of volatile memory include static random access memory (SRAM) and dynamic random access memory (DRAM).
Non-volatile memory is generally used to store data that needs to be saved for long periods of time or needs some degree of security. Examples of such data are BIOS, program code, and system software. Non-volatile memory devices include read only memory (ROM), EPROM, EEPROM, flash, magnetic storage media, compact disks, laser disks, and optical disks.
Some memory cells have been developed that include both a volatile memory circuit and a non-volatile memory circuit. For example, U.S. Pat. No. 4,510,584, U.S. Pat. No. 4,538,246, U.S. Pat. No. 4,638,465, and U.S. Pat. No. 5,353,248, disclose memory cells having a non-volatile circuit that stores the state of a volatile circuit such that data stored in the volatile memory circuit is not lost when power is removed from the memory cell. The size of these memory cells is larger than the size of conventional volatile memory cells to accommodate the additional non-volatile circuitry. Thus, the number of memory cells including both volatile and non-volatile circuits is less than the number of conventional volatile memory cells per area of silicon.
Additionally, complex circuitry or additional power supply voltages may be required to control the operation of conventional memory cells having volatile and non-volatile memory circuits. The circuits may require additional commands to invoke their operation or additional power supply voltages to program the non-volatile memory circuit of the memory cell.
U.S. Pat. No. 5,923,582 discloses a memory device with a combination of a first block of RAM cells having preprogrammed states, and a second block of conventional random access memory cells. A select circuit is configured to reset the first block of RAM cells to their preprogrammed states. The desired ROM code is stored in the first block of RAM cells by unbalancing transistors in the cells so that the cells power up in the desired predetermined state consistent with the ROM code to be stored in the first block of RAM cells. The select circuit alters the power applied to the first block of RAM cells to cause the RAM cells to power up with the ROM code. Thus, the first block of RAM cells are configured to operate as both a volatile and nonvolatile memory cell using the same cell structure.
U.S. Pat. No. 6,765,818 discloses a static CMOS RAM with memory cells with cross-coupled inverters and wherein some of the cells operate as ROM cells by connection of an input of one of the inverters of each cell to one of a fixed low electric potential and a fixed high electric potential and connection of the output of the inverter to the input of the other inverter of the respective cell.